0977774ワット発電中さん
2016/10/19(水) 19:07:45.88ID:7FziahEkoutput reset ;//1-active
reg [1:0] locked_d;
always@(posedge clk or negedge locked) begin
if(locked == 1'b0)
locked_d <= 2'b00;
else
locked_d <= {locked_d[0], locked};
end
assign reset = ~locked_d[1];